HI3338KIBZ【PDF 6/9 页】IC DAC 8BIT CMOS 16-SOIC

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If the code into an 8-bit D/A is changed by 1 count, the

output should change by 1/255 (full-scale output-zero scale

output). A deviation from this step size is a differential

linearity error, see Figure 4. Note that the error is expressed

in fractions of the ideal step size (usually called an LSB).

Also note that if the (-) differential linearity error is less (in

absolute numbers) than 1 LSB, the device is monotonic.

(The output will always increase for increasing code or

decrease for decreasing code).

If the code into an 8-bit D/A is at any value, say “N”, the

output voltage should be N/255 of the full-scale output

(referred to the zero-scale output). Any deviation from that

output is an integral linearity error, usually expressed in

LSBs. See Figure 4.

Note that OFFSET and GAIN errors do not affect integral

linearity, as the linearity is referenced to actual zero and full

scale outputs, not ideal. Absolute accuracy would have to

also take these errors into account.

Dynamic Characteristics

Keeping the full-scale range (VREF+ - VREF-) as high as

possible gives the best linearity and lowest “glitch” energy

(referred to 1V). This provides the best “P” and “N” channel

gate drives (hence saturation resistance) and propagation

delays. The VREF+ (and VREF- if bipolar) terminal should be

well bypassed as near the chip as possible.

“Glitch” energy is defined as a spurious voltage that occurs

as the output is changed from one voltage to another. In a

binary input converter, it is usually highest at the most

significant bit transition (7FHEX to 80HEX for an 8-bit device),

and can be measured by displaying the output as the input

code alternates around that point. The “glitch” energy is the

area between the actual output display and an ideal one LSB

step voltage (subtracting negative area from positive), at

either the positive or negative-going step. It is usually

expressed in pV-s.

The HI3338 uses a modified R2R ladder, where the 3 most

significant bits drive a bar graph decoder and 7 equally

weighted resistors. This makes the “glitch” energy at each 1/8

scale transition (1FHEX to 20HEX, 3FHEX to 40HEX, etc.)

essentially equal, and far less than the MSB transition would

otherwise display.

For the purpose of comparison to other converters, the

output should be resistively divided to 1V full scale. Figure 5

shows a typical hook-up for checking “glitch” energy or

settling time.

The settling time of the A/D is mainly a function of the output

resistance (approximately 160

in parallel with the load

resistance) and the load plus internal chip capacitance. Both

“glitch” energy and settling time measurements require very

good circuit and probe grounding: a probe tip connector such

as Tektronix part number 131-0258-00 is recommended.

255/256

254/256

253/256

3/256

2/256

1/256

= IDEAL TRANSFER CURVE

= ACTUAL TRANSFER CURVE

OFFSET

ERROR

(SHOWN +)

OUT

ION

REF

GAIN ERROR (SHOWN -)

INPUT CODE IN HEXADECIMAL (COMP = LOW)

FIGURE 3. D/A OFFSET AND GAIN ERROR

OUT

FROM “0” SCALE

INTEGRAL LINEARITY

ERROR (SHOWN -)

STRAIGHT LINE

TO FULL SCALE

VOLTAGE

INPUT CODE

= IDEAL TRANSFER CURVE

= ACTUAL TRANSFER CURVE

A = IDEAL STEP SIZE (1/255 OF FULL

B - A = +DIFFERENTIAL LINEARITY ERROR

C - A = -DIFFERENTIAL LINEARITY ERROR

SCALE -“0” SCALE VOLTAGE)

FIGURE 4. D/A INTEGRAL AND DIFFERENTIAL LINEARITY

TABLE 1. OUTPUT VOLTAGE vs INPUT CODE AND VREF

VREF+

VREF-

STEP SIZE

5.12V

0.0200V

5.00V

0.0195V

4.608V

0.0180V

2.56V

-2.56V

0.0200V

2.50V

-2.50V

0.0195V

Input Code

111111112 = FFHEX

111111102 = FEHEX

5.1000V

5.0800

4.9805V

4.9610

4.5900V

4.5720

2.5400V

2.5200

2.4805V

2.4610

100000012 = 81HEX

100000002 = 80HEX

011111112 = 7FHEX

2.5800

2.5600

2.5400

2.5195

2.5000

2.4805

2.3220

2.3040

2.2860

0.0200

0.0000

- 0.0200

0.0195

0.0000

-0.0195

000000012 = 01HEX

000000002 = 00HEX

0.0200

0.0000

0.0195

0.0000

0.0180

0.0000

-2.5400

-2.5600

-2.4805

-2.5000

HI3338

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